HW-V5-ML555-G【PDF 62/108 页】BOARD EVAL FOR VIRTEX-5 ML555

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Chapter 3: Hardware Description

Table 3-21:

ICS8442 Divisor Switch Settings

R

SW12-9 or

SW12-10 (2)

“N1”

SW10-9 or

SW12-11 (3)

“N0”

Output Divisor

Value

Output Frequency (MHz)

Minimum Maximum

0

0

1

1

0

1

0

1

1

2

4

8

250

125

62.5

31.25

700

350

175

87.5

Notes:

1. A logic “0” is obtained by moving the switch to the “OPEN” position, and a logic “1” is obtained by

moving the switch to the “CLOSED” position.

2. SW12-9 is for the N1 input of Clock Synthesizer 1, and SW12-10 is for the N1 input of Clock

Synthesizer 2.

3. SW10-9 is for the N0 input of Clock Synthesizer 1, and SW12-11 is for the N0 input of Clock Synthesizer

2.

Parallel Mode Operation

Each clock synthesizer has one set of subminiature DIP switches to set the multiplier and

divider settings in parallel mode. Clock Synthesizer 1, with a 10 MHz reference clock

input, can be set to 0x019 through 0x046 , as shown in Table 3-22, page 64 . Clock

Synthesizer 2, with a 25 MHz reference clock input, can be set to 0x00A through 0x01C , as

shown in Table 3-23, page 66 . DIP switches are provided on the board to allow user

selection of multiplier values that result in valid VCO lock ranges. Multiplier bits that

would result in a VCO unlock condition are hardwired to a logic 0 level on the board.

Figure 3-11 shows the locations of the switches for both synthesizers.

62

Virtex-5 FPGA ML555 Development Kit

UG201 (v1.4) March 10, 2008

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